TNETV1002IDZHK datasheet(96/102 Pages) TI1

96 / 102 page

Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

Table 6--40. SPI Rising Edge Timing Requirements

MIN

NOM

MAX

UNIT

td(ENRS--CLKH)

Delay time, Rising enable start active to first clock high

A-- 3†

A†

A+ 3†

td(CLKL--ENRE)

Delay time, Last clock low to rising enable end

A/2 -- 3†

A/2†

A/2 + 3†

tw(ENRT)

Pulse duration, Rising enable toggle

A-- 3†

A†

A+ 3†

td(CLKL--DOV)

Delay time, Clock low to data out valid

tsu(DIV--CLKH)

Setup time, Data in valid to clock high

th(CLKH--DIIV)

Hold time, Clock high to data in invalid

† A= 4 x PTVx tc(ARM)

In this mode, all timing related activity for Data In and Enable is based on the falling edge of the SPI Clock.

The timing activity for Data Out will be based on the rising edge of the SPI clock.

MSB

LSB

Bit=31

Bit=32--total

MCUENO, 1 2,

(negative edge

triggered)

MCUENO, 1 2,

(positive edge

triggered)

(negative level

triggered)

MCUENO, 1 2,

triggered)

(positive level

CLKX_SPI

MCUDO

MCUDI

MSB

LSB

Bit=total--1

Bit=0

td(ENRS- CLKH)

td(CLKL- ENRE)

tw(ENRT)

th(CLKH- DIIV)

tsu(DIV- CLKH)

td(CLKL- DOV)

tc(SPI)

tw(SPI- H)

tw(SPI- L)

tr(SPI)

tf(SPI)

Figure 6--38. SPI Rising Edge Timings

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