M38B53M4-059FP datasheet(266/355 Pages) MITSUBISHI

266 / 355 page

3-18

APPENDIX

38B5 Group User’s Manual

3.3 Notes on use

Fig. 3.3.4 Sequence of setting serial I/O2 control register again

(4)

Setting serial I/O2 control register again

Set the serial I/O2 control register again after the transmission and the reception circuits are reset

by clearing both the transmit enable bit and the receive enable bit to “0.”

(5)

Data transmission control with referring to transmit shift register completion flag

The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift

clocks. When data transmission is controlled with referring to the flag after writing the data to the

transmit buffer register, note the delay.

(6)

Transmission control when external clock is selected

When an external clock is used as the synchronous clock for data transmission, set the transmit

enable bit to “1” at “H” of the serial I/O2 clock input level. Also, write the transmit data to the transmit

buffer register (serial I/O shift register) at “H” of the serial I/O2 clock input level.

(7)

Transmit interrupt request when transmit enable bit is set

The transmission interrupt request bit is set and the interruption request is generated even when

selecting timing that either of the following flags is set to “1” as timing where the transmission

interruption is generated.

• Transmit buffer empty flag is set to “1”

• Transmit shift register completion flag is set to “1”

Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit

enabled as the following sequence.

Transmit enable bit is set to “1”

Transmit interrupt request bit is set to “0”

q Reason

When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift

(8)

Using TxD pin

The P55/TxD P-channel output disable bit of UART control register is valid in both cases: using as

a normal I/O port and as the TxD pin. Do not supply Vcc + 0.3 V or more even when using the P55/

TxD pin as an N-channel open-drain output.

Additionally, in the serial I/O2, the TxD pin latches the last bit and continues to output it after

completing transmission.

Clear both the transmit enable

bit (TE) and the receive enable

bit (RE) to “0”

↓

Set the bits 0 to 3 and bit 6 of the

serial I/O2 control register

↓

Set both the transmit enable bit

(TE) and the receive enable bit

(RE), or one of them to “1”

Can be set with the

LDM instruction at

the same time

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