DS3134 datasheet(22/203 Pages) DALLAS

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DS3134

22 of 203

Lead

Symbol

Type

Signal Description

VSS

Ground Reference.

U12

VSS

Ground Reference.

U13

VSS

Ground Reference.

U17

VSS

Ground Reference.

2.2 SERIAL PORT INTERFACE SIGNAL DESCRIPTION

Signal Name:

RC0 / RC1 / RC2 / RC3 / RC4 / RC5 / RC6 / RC7 / RC8 / RC9 / RC10 / RC11 /

RC12 / RC13 / RC14 / RC15

Signal Description:

Receive Serial Clock

Signal Type:

Input

Data can be clocked into the device either on falling edges (normal clock mode) or rising edges (inverted

clock mode) of RC. This is programmable on a per port basis. RC0 & RC1 can operate at speeds up to

52 MHz. RC2 to RC15 can operate at speeds up to 10 MHz. If not used, should be tied low.

Signal Name:

RD0 / RD1 / RD2 / RD3 / RD4 / RD5 / RD6 / RD7 / RD8 / RD9 / RD10 / RD11 /

RD12 / RD13 / RD14 / RD15

Signal Description:

Receive Serial Data

Signal Type:

Input

Can be sampled either on the falling edge of RC (normal clock mode) or the rising edge of RC (inverted

clock mode). If not used, should be tied low.

Signal Name:

RS0 / RS1 / RS2 / RS3 / RS4 / RS5 / RS6 / RS7 / RS8 / RS9 / RS10 / RS11 /

RS12 / RS13 / RS14 / RS15

Signal Description:

Receive Serial Data Synchronization Pulse

Signal Type:

Input

A one RC clock wide synchronization pulse that can be applied to the Chateau to force byte/frame

alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low

(inverted sync mode). The RS signal can be sampled either on the falling edge or on rising edge of RC

(see Table 2.2A below for details). The applied sync pulse can be during the first RC clock period of a

193/256/512/1024 bit frame or it can be applied 1/2, 1, or 2 RC clocks early. This input sync signal resets

a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096 MHz mode)

or 1024 (8.192 MHz mode) RC clocks. It is acceptable to only pulse the RS signal once to establish byte

boundaries and allow Chateau to keep track of the byte/frame boundaries by counting RC clocks. If the

incoming data does not require alignment to byte/frame boundaries, then this signal should be tied low.

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