DS3134 datasheet(48/203 Pages) DALLAS

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DS3134

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will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the

Local Bus is in the Configuration Mode.

Bit 5 / Status Bit for Receive FIFO Overflow (ROVFL). This status bit will be set to a one if any of

the HDLC channels experiences an overflow in the receive FIFO. The ROVFL bit will be cleared when

read and will not be set again until another overflow has occurred. If enabled via the ROVFL bit in the

Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus

via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.

Bit 6 / Status Bit for Receive DMA Large Buffer Read (RLBR). This status bit will be set to a one

each time the Receive DMA completes a single read or a burst read of the Large Buffer Free Queue. The

RLBR bit will be cleared when read and will not be set again, until another read of the Large Buffer Free

Queue has occurred. If enabled via the RLBR bit in the Interrupt Mask for SDMA (ISDMA), the setting

of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT*

if the Local Bus is in the Configuration Mode.

Bit 7 / Status Bit for Receive DMA Large Buffer Read Error (RLBRE). This status bit will be set to

a one each time the Receive DMA tries to read the Large Buffer Free Queue and it is empty. The RLBRE

bit will be cleared when read and will not be set again, until another read of the Large Buffer Free Queue

detects that it is empty. If enabled via the RLBRE bit in the Interrupt Mask for SDMA (ISDMA), the

setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the

LINT* if the Local Bus is in the Configuration Mode.

Bit 8 / Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit will be set to a one

each time the Receive DMA completes a single read or a burst read of the Small Buffer Free Queue. The

RSBR bit will be cleared when read and will not be set again, until another read of the Small Buffer Free

Queue has occurred. If enabled via the RSBR bit in the Interrupt Mask for SDMA (ISDMA), the setting

of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT*

if the Local Bus is in the Configuration Mode.

Bit 9 / Status Bit for Receive DMA Small Buffer Read Error (RSBRE). This status bit will be set to a

one each time the Receive DMA tries to read the Small Buffer Free Queue and it is empty. The RSBRE

bit will be cleared when read and will not be set again, until another read of the Small Buffer Free Queue

detects that it is empty. If enabled via the RSBRE bit in the Interrupt Mask for SDMA (ISDMA), the

setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the

LINT* if the Local Bus is in the Configuration Mode.

Bit 10 / Status Bit for Receive DMA Done Queue Write (RDQW). This status bit will be set to a one

when the Receive DMA writes to the Done Queue. Based of the setting of the Receive Done Queue

Threshold Setting (RDQT0 to RDQT2) bits in the Receive DMA Queues Control (RDMAQ) register, this

bit will be set either after each write or after a programmable number of writes from 2 to 128. See

Section 8.1.4 for more details. The RDQW bit will be cleared when read and will not be set again until

another write to the Done Queue has occurred. If enabled via the RDQW bit in the Interrupt Mask for

SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA*

signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.

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