MCP3918A1-ESLASHML datasheet(22/88 Pages) MICROCHIP

22 / 88 page

MCP3918

DS20005287A-page 22

 2014 Microchip Technology Inc.

3.13

Chip Select/ Boost Logic Input

(CS/BOOST)

In SPI mode, this pin is the SPI chip select that enables

serial communication. When this pin is logic high, no

communication can take place. A chip select falling

edge initiates serial communication, and a chip select

rising edge terminates the communication. No

communication can take place even when CS is logic

low, if RESET is also logic low.

This input is Schmitt-triggered.

In the 2-Wire Interface mode, this is the Boost logic

select pin. See Section 7.0 “2-Wire Serial Interface

Description”

for the logic input table for Boost. The pin

state is latched when the mode changes to 2-Wire

Interface mode, and is re-latched at each watchdog

timer reset.

3.14

Serial Data Clock/

Master Clock Input (SCK/MCLK)

In SPI mode, this is the serial clock pin for SPI

communication. Data is clocked into the device on the

rising edge of SCK. Data is clocked out of the device on

the falling edge of SCK.

The MCP3918 SPI interface is compatible with SPI 0,0

and 1,1 modes. SPI modes can be changed during a

CS high time.

The maximum clock speed specified is 20 MHz. SCK

and MCLK are two different and asynchronous clocks;

SCK is only required when a communication happens,

while MCLK is continuously required when the part is

converting analog inputs.

This input is Schmitt-triggered.

In the 2-Wire Interface mode, this pin is defining the

master clock of the device (MCLK) and the serial clock

(SCK) for the interface simultaneously. In this mode,

the clock has to be provided continuously to ensure

proper operation. See Section 7.0 “2-Wire Serial

Interface Description”

for more information and

timing diagrams of the 2-Wire interface protocol.

3.15

Serial Data Output (SDO)

This is the SPI data output pin. Data is clocked out of

the device on the falling edge of SCK.

This pin remains in a high-impedance state during the

command byte. It also stays high-impedance during the

entire communication for Write commands and when

the CS pin is logic high or when the RESET pin is logic

low. This pin is active only when a Read command is

processed. The interface is half-duplex (inputs and

outputs do not happen at the same time).

In the 2-Wire Interface Mode, this pin is the only digital

output pin, and sends synchronous frames at each

data ready with data bits clocked out on the falling edge

of SCK.

3.16

Serial Data/OSR1 Logic Input

(SDI/OSR1)

In SPI mode, this is the SPI data input pin. Data is

clocked into the device on the rising edge of SCK.

When CS is logic low, this pin is used to communicate

with 8-bit commands followed by data bytes that can be

16-/24- or 32-bit wide. The interface is half-duplex

(inputs and outputs do not happen at the same time).

Each communication starts with a chip select falling

edge followed by an 8-bit command word, entered

through the SDI pin. Each command is either a Read or

a Write command. Toggling SDI during a Read

command has no effect.

This input is Schmitt-triggered.

In 2-Wire Interface mode, this is the OSR1 logic select

pin. See Section 7.0 “2-Wire Serial Interface

Description”

for the logic input table for OSR0 and

OSR1. The pin state is latched when the mode

changes to 2-Wire Interface Mode, and is relatched at

each watchdog timer reset.

3.17

Exposed Pad (EP)

Exposed Thermal Pad. This pin must be connected to

AGND for optimal accuracy and thermal performance.

This pad can also be left floating if necessary.

Connecting it to AGND is preferable for the lowest noise

performance and best thermal behavior.

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