MCP3918A1-ESLASHML datasheet(40/88 Pages) MICROCHIP

40 / 88 page

MCP3918

DS20005287A-page 40

 2014 Microchip Technology Inc.

5.10

Data Ready Status Bit

In addition to the DR pin indicator, the MCP3918 device

includes a separate Data Ready status bit. The ADC

channel

associated

the

corresponding

DRSTATUS bit that can be read at all times in the

STATUSCOM register. This status bit can be used to

synchronize the data retrieval, in case the DR pin is not

connected (see Section 6.8 “ADC Channel Latching

and Synchronization”

The DRSTATUS bit is not writable; writing on it has no

effect. It has a default value of '1', which indicates that

the data of the corresponding ADC is not ready. This

means that the ADC output register has not been

updated since the last reading (or since the last reset).

The DRSTATUS bit takes the '0' state, once the ADC

channel register is updated (which happens at a

DRCLK rate). A simple read of the STATUSCOM

('1').

5.11

Crystal Oscillator

The MCP3918 includes a Pierce-type crystal oscillator

with very high stability and ensures very low tempco

and jitter for the clock generation. This oscillator can

handle crystal frequencies up to 20 MHz, provided that

proper load capacitances and quartz quality factor are

used. The crystal oscillator is enabled when

CLKEXT = 0 in the CONFIG1 register, therefore it

cannot be enabled during the 2-Wire Interface mode. It

is only selectable in the SPI Mode.

For a proper start-up, the load capacitors of the crystal

should be connected between OSC1 and DGND and

between OSC2 and DGND. They should also respect

Equation 5-7.

EQUATION 5-7:

When CLKEXT = 1, the crystal oscillator is bypassed

by a digital buffer, to allow direct clock input for an

external clock (see Figure 4-1). In this case, OSC2

becomes the MODE select input pin for the Interface

mode. When MODE = 0, the digital interface stays in

SPI mode; when MODE = 1, the digital interface

toggles to the 2-Wire mode. A pull-down current forces

the MODE to be logic low (SPI mode) by default if the

OSC2 pin is floating.

For proper operation, the external clock should not be

higher

than

20 MHz

before

prescaling

(MCLK < 20 MHz).

TABLE 5-9:

PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 4096,

PRE<1:0> = 00

PHASE<11:0>

Hex

Delay

0111 111111 11

0x7FF

4095 µs

0111 111111 10

0x7FE

4094 µs

0000 000000 01

0x001

2049 µs

0000 000000 00

0x000

2048 µs

1111 111111 11

0xFFF

2047 µs

1000 000000 01

0x801

1 µs

1000 000000 00

0x800

0 µs

Note:

In addition to the conditions defining the

maximum MCLK input frequency range,

the

AMCLK

frequency

should

maintained inferior to the maximum limits

defined in Table 5-2, to ensure the

accuracy of the ADC. If these limits are

exceeded, it is recommended to choose

either a larger OSR or a larger prescaler

value so that AMCLK can respect these

limits.

1.6



LOAD

-------------------------







Where:

f = crystal frequency in MHz

CLOAD = load capacitance in pF, including

parasitics from the PCB

RM = motional resistance of the quartz, in

ohms

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