STM32F446VC datasheet(150/202 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F446xC/E

150/202

DocID027107 Rev 6

INL(4)

Integral non

linearity (difference

between

measured value at

Code i and the

value at Code i on

a line drawn

between Code 0

and last Code

1023)

±1

LSB

Given for the DAC in 10-bit

configuration.

±4

LSB

Given for the DAC in 12-bit

configuration.

Offset(4)

Offset error

(difference

between

measured value at

Code (0x800) and

the ideal value =

VREF+/2)

±10

Given for the DAC in 12-bit

configuration

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

±12

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

Gain

error(4)

Gain error

±0.5

Given for the DAC in 12-bit

configuration

tSETTLING(4

)

Total Harmonic

Distortion

Buffer ON

µs

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

THD(4)

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

Update

rate(2)

Max frequency for

a correct

DAC_OUT change

when small

variation in the

input code (from

code i to i+1LSB)

MS/

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

tWAKEUP(4)

Wakeup time from

off state (Setting

the ENx bit in the

DAC Control

6.5

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest

and highest possible ones.

PSRR+ (2)

Power supply

rejection ratio (to

VDDA) (static DC

measurement)

- 67

- 40

dB No RLOAD, CLOAD = 50 pF

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:

Internal reset OFF).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed based on test during characterization.

Table 85. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Comments

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