BLUENRG-1 datasheet(83/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

DocID028866 Rev 1

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3.10.2.2

I²C clock rate calculation

To define the I2C clock rate generation there is one register to configure: BRCR. The clock

rate can be calculated using this formula:

Where:



fI2C is the I2C peripheral clock, clocked on the system clock divided by 3.



BRCNT2 is a field of the BRCR register.



Foncycle depends on a programmable field of the CR register:



CR: FON = “00” => Filter the clock spike wide = 0 => Foncycle = 1



CR: FON = “01” => Filter the clock spike wide = 1 => Foncycle = 3



CR: FON = “10” => Filter the clock spike wide = 2 => Foncycle = 4



CR: FON = “11” => Filter the clock spike wide = 4 => Foncycle = 6

The minimum input clock frequency for the I2C is:



1.4 MHz if the I2C is in standard mode at 100 kHz.



7.2 MHz if the I2C is in fast mode at 400 kHz.

3.10.2.3

I²C configuration

Following a Reset, the I2C logic is disabled and must be configured when in this state.

The control register (CR) and baud rate register (BRCR) need to be programmed to

configure the following parameters of the peripheral:



Master or slave.



7- or 10-bit addressing mode



Speed mode



Clock rate

If in slave mode, the SCR register has to be programmed with the selected slave

address.

Then, if in master mode, the MCR register is used to define the transaction:



Read or write.



Slave addresses (7- or 10-bit) to communicate with.



Addressing a 7- or 10-bit slave address.



Stop condition, to generate a stop or restart condition at the end of the transaction (for

consecutive transactions).



Transaction length

For a master write, the data to transmit have to be written to the transmit FIFO in

the I2C_TFR register. For a master read, when the master transaction is done,

data are available in the receive FIFO in I2C_RFR.

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