BLUENRG-1 datasheet(40/173 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-1

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does not support byte or halfword write operations (when HSIZE is not used by the

peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as

shown in the two examples below:



To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD”

with HSIZE = HalfWord



To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with

HSIZE = Byte

Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the

HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit

APB operation in the following manner:



an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be

converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0



an AHB half-

word write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be

converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0

3.7.2.5

Error management

A DMA transfer error can be generated by reading from or writing to a reserved address

space. When a DMA transfer error occurs during a DMA read or a write access, the faulty

channel is automatically disabled through a hardware clear of its EN bit in the

corresponding Channel configuration register (DMA_CCRx). The channel's transfer error

interrupt flag (TEIF) in the ISR register is set and an interrupt is generated if the transfer

error interrupt enable bit (TEIE) in the DMA_CCRx register is set.

3.7.2.6

Interrupts

An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for

each DMA channel. Separate interrupt enable bits are available for flexibility.

Table 36: DMA interrupt requests

Interrupt event

Event flag

Enable control bit

Half-transfer

HTIF

HTIE

Transfer complete

TCIF

TCIE

Transfer error

TEIF

TEIE

3.7.2.7

DMA request mapping

The eight requests from the peripherals (SPI, I2Cx[1,2] and UART) are multiplexed before

entering DMA with the ADC request. For each channel, the choice between the peripheral

and the ADC is done through the DMA_CONFIG register.

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