DS00002142A-page 23

USB3250

7.5

RX Logic

This block receives serial data from the CRC block and processes it to be transferred to the SIE on the RXDATA bus.

The processing involved includes NRZI decoding, bit unstuffing, and serial to parallel conversion. Upon valid assertion

of the proper RX control lines by the RX State Machine, the RX Logic block will provide bytes to the RXDATA bus as

shown in the figures below. The behavior of the Receive State Machine is described below.

FIGURE 7-7:

RECEIVE TIMING FOR DATA WITH UNSTUFFED BITS (8-BIT MODE)

FIGURE 7-8:

RECEIVE TIMING FOR 16-BIT DATA, EVEN BYTE COUNT

DATA

Data

DATA

CRC

CRC

Invalid Data

DATA

DATA

DATA

Invalid

Invalid

CLK60

RXACTIVE

RXDATA[7:0]

RXVALID

CLK30

DATA[7:0]

RXACTIVE

RXVALID

DP/DM

PID

DATA

DATA

DATA

DATA

DATA

CRC

CRC

PID

DATA[15:8]

DATA (0)

DATA

(1)

DATA (2)

DATA (3)

DATA (4)

CRC (LO)

01

2

3

4

LO

VALIDH

CRC (HI)

EOP

HI

SYNC