USB3250

DS00002142A-page 32

Note 8-1

T0 may occur to 4ms after HS Reset T0.

Note 8-2

The SIE must assert the Chirp K for 66000 CLK60 cycles to ensure a 1ms minimum duration.

8.9

HS Detection Handshake - HS Downstream Facing Port

Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is

asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding,

XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1).

The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device

begins listening for a chirp sequence from the downstream facing port. If the downstream facing port is HS capable then

it will begin generating an alternating sequence of Chirp K's and Chirp J's (T3) after the termination of the chirp from the

device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it will enter HS mode by setting

TERMSELECT to HS mode (T7).

Figure 8-4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the device port must

terminate the sequence of Chirp K's and Chirp J's (T8) and assert SE0 (T8-T9). Note that the sequence of Chirp K's and

Chirp J's constitutes bus activity.

TABLE 8-6:

HS DETECTION HANDSHAKE TIMING VALUES (FS MODE)

Timing Parameter

Description

Value

T0

HS Handshake begins. DP pull-up enabled, HS

terminations disabled. The XCVRSELECT and

OPMODE inputs are then set for HS with bitstuffing

disabled, and TXVALID is asserted at least 5 60MHz

clocks later.

0 (reference)

T1

Device enables HS Transceiver and asserts Chirp K on

the bus.

T0 < T1 < HS Reset T0 + 6.0ms

T2

Device removes Chirp K from the bus. 1ms minimum

width.

T1 + 1.0 ms < T2 < HS Reset T0 +

7.0ms

T3

Earliest time when downstream facing port may assert

Chirp KJ sequence on the bus.

T2 < T3 < T2+100µs

T4

Chirp not detected by the device. Device reverts to FS

default state and waits for end of reset.

T2 + 1.0ms < T4 < T2 + 2.5ms

T5

Earliest time at which host port may end reset

HS Reset T0 + 10ms