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LAN9211 데이터시트(PDF) 44 Page - SMSC Corporation

부품명 LAN9211
상세설명  High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
PDF  147 Pages
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제조업체  SMSC [SMSC Corporation]
홈페이지  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN9211 데이터시트(HTML) 44 Page - SMSC Corporation

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
Revision 2.9 (03-01-12)
44
SMSC LAN9211
DATASHEET
Note 3.10 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
setting of PME_EN.
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9211 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host
is required to check the READY bit and verify that it is set before attempting any other reads or writes
of the device. Before the LAN9211 is fully awake from this state the EDPWRDOWN bit in register 17
of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit
until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9211 is ready to resume normal
operation. At this time the WUPS field can be cleared.
Table 3.10 Power Management States
Device
BLOCK
D0
(NORMAL OPERATION)
D1
(WOL)
D2
(ENERGY DETECT)
PHY
Full ON
Full ON
Energy Detect Power-Down
MAC Power
Management
Full ON
RX Power Mgmt. Block
On
OFF
MAC and Host
Interface
Full ON
OFF
OFF
Internal Clock
Full ON
Full ON
OFF
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF



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