LAN9211 datasheet(54/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

3.12.5

Calculating Actual TX Data FIFO Usage

The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet:

TX command 'A' is stored in the TX data FIFO for every TX buffer.

TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX

command 'A.'

When TX checksum is enabled, the 4-byte TX checksum preamble is written into TX Data FIFO.

Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before

the data is written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX

data FIFO.

Payload from each buffer within a Packet is written into the TX data FIFO.

Any DWORD-long data added as part of the End Padding is removed from each buffer before the

data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the

TX data FIFO.

No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present

during transmission.

Note:

During 10/100 Mbps full-duplex transmission, the value of this bit is invalid and should be

ignored.

Late Collision. When set, indicates that the packet transmission was aborted after the collision

window of 64 bytes.

Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16

collisions while attempting to transmit the current packet.

Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.

6:3

Collision Count. This counter indicates the number of collisions that occurred before the packet was

transmitted. It is not valid when excessive collisions (bit 8) is also set.

Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive

deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times

during transmission.

Reserved. This bit is reserved. Always write zero to this bit to guarantee future compatibility.

Deferred. When set, this bit indicates that the current packet transmission was deferred.

BITS

DESCRIPTION

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