LAN9211 datasheet(84/147 Pages) SMSC

84 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

5.3.5

BYTE_TEST—Byte Order Test Register

This register can be used to determine the byte ordering of the current configuration

5.3.6

FIFO_INT—FIFO Level Interrupts

This register configures the limits where the FIFO Controllers will generate system interrupts.

Offset:

64h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Byte Test

87654321h

Offset:

68h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31-24

TX Data Available Level. The value in this field sets the level, in number

of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be

generated. When the TX data FIFO free space is greater than this value a

TX FIFO Available interrupt (TDFA) will be generated.

R/W

48h

23-16

TX Status Level. The value in this field sets the level, in number of

DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be

generated. When the TX Status FIFO used space is greater than this value

an TX Status FIFO Level interrupt (TSFL) will be generated.

R/W

00h

15-8

Reserved

7-0

RX Status Level. The value in this field sets the level, in number of

DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be

generated. When the RX Status FIFO used space is greater than this value

an RX Status FIFO Level interrupt (RSFL) will be generated.

R/W

00h

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