MLX71122_16 datasheet(27/59 Pages) MELEXIS

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MLX71122

300 to 930MHz FSK/FM/ASK Receiver

Datasheet

REVISION 014 – AUGUST, 2016

Page 27 of 59

390 10 71122 01

Typical VCO Gain

Band / MHz

L0 inductor / nH

KVCO / MHz/V, VCCRANGE=0

KVCO / MHz/V, VCCRANGE=1

315

128

434

188

868

5.6

222

108

915

5.6

250

116

The phase margin ΦM determines the stability of the PLL. It should be larger than 45°. A phase margin of

56.4° should be preferred.

The closed loop PLL bandwidth fC of a receiver should be as large as possible in order to allow fast settling

of the frequency. On the other hand it should be so low that the reference spurs at the PFD frequency are

sufficiently suppressed. A good compromise is to make fC 1/10 of the PFD frequency. Therefore it is

desirable to make fPFD as large as possible or the R divider as small as possible but not smaller than 20.

The feedback ratio between the VCO output frequency and the PFD frequency shall be called N.

The following empirically derived formulas are rules of thumb for a phase margin of 56.4° and for

receivers.

ωU shall be the unity gain bandwidth in rad/s of the open loop PLL transfer function.



 

(19)

VCO







(20)



(21)





(22)







(23)

The loop filter elements for 868 and 915MHz in the evaluation board list in section 6.3 are scaled values of

the calculated values in order to reduce the capacitance value. If the capacitors are scaled down then the

resistor needs to be scaled up by the same factor and vice versa.

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