MB95F613H datasheet(44/110 Pages) CYPRESS

44 / 110 page

Document Number: 002-04698 Rev. *A

Page 44 of 110

PRELIMINARY

MB95610H Series

15.2.4 Port 1 operations

■ Operation as an output port

❐ A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”.

❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.

❐ When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.

❐ If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is.

❐ Reading the PDR1 register returns the PDR1 register value.

■ Operation as an input port

❐ A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.

❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.

❐ If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port.

❐ Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the

PDR1 register, the PDR1 register value is returned.

■ Operation as a peripheral function output pin

❐ A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a

peripheral function corresponding to that pin.

❐ The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value

of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type

of instruction is used to read the PDR1 register, the PDR1 register value is returned.

■ Operation as a peripheral function input pin

❐ To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”.

❐ Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.

However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned.

■ Operation at reset

If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled.

■ Operation in stop mode and watch mode

❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P14/UCK0 and

P15/UI0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin

selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.

❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

■ Operation of the pull-up register

Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level,

the pull-up resistor is disconnected regardless of the value of the PUL1 register.

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