MB95F613H datasheet(96/110 Pages) CYPRESS

96 / 110 page

Document Number: 002-04698 Rev. *A

Page 96 of 110

PRELIMINARY

MB95610H Series

(Continued)

(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)

*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.

*2: • See “(2) Source Clock/Machine Clock” for tMCLK.

• m represents the CS[4:3] bits in the I2C clock control register ch. 0 (ICCR0).

• n represents the CS[2:0] bits in the I2C clock control register ch. 0 (ICCR0).

• The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK) and the

CS[4:0] bits in the ICCR0 register.

• Standard-mode:

m and n can be set to values in the following range: 0.9 MHz

 tMCLK (machine clock)  16.25 MHz.

The usable frequencies of the machine clock are determined by the settings of m and n as shown below.

(m, n) = (1, 8)

: 0.9 MHz < tMCLK  1 MHz

(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)

: 0.9 MHz < tMCLK  2 MHz

(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)

: 0.9 MHz < tMCLK  4 MHz

(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)

: 0.9 MHz < tMCLK  10 MHz

(m, n) = (8, 22)

: 0.9 MHz < tMCLK  16.25 MHz

• Fast-mode:

m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.

The usable frequencies of the machine clock are determined by the settings of m and n as shown below.

(m, n) = (1, 8)

: 3.3 MHz < tMCLK  4 MHz

(m, n) = (1, 22), (5, 4)

: 3.3 MHz < tMCLK  8 MHz

(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)

: 3.3 MHz < tMCLK  10 MHz

(m, n) = (5, 8)

: 3.3 MHz < tMCLK  16.25 MHz

Parameter

Symbol

name

Condition

Value*2

Unit

Remarks

Min

Max

START condition

detection

tHD;STA

SCL,

SDA

R = 1.7 k

,

C = 50 pF*1

2 tMCLK  20

—

No START condition is detected

when 1 tMCLK is used at reception.

STOP condition

detection

tSU;STO

SCL,

SDA

2 tMCLK  20

—

No STOP condition is detected when

1 tMCLK is used at reception.

RESTART condition

detection condition

tSU;STA

SCL,

SDA

2 tMCLK  20

—

No RESTART condition is detected

when 1 tMCLK is used at reception.

Bus free time

tBUF

SCL,

SDA

2 tMCLK  20

—

At reception

Data hold time

tHD;DAT

SCL,

SDA

2 tMCLK  20

—

At slave transmission mode

Data setup time

tSU;DAT

SCL,

SDA

tLOW  3 tMCLK  20

—

At slave transmission mode

Data hold time

tHD;DAT

SCL,

SDA

—

At reception

Data setup time

tSU;DAT

SCL,

SDA

tMCLK  20

—

At reception

SDA

  SCL

(with wakeup function

in use)

tWAKEUP

SCL,

SDA

Oscillation stabilization wait

time

2 tMCLK  20

—ns

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