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MB95F613K 데이터시트(PDF) 95 Page - Cypress Semiconductor

부품명 MB95F613K
상세설명  F2MC-8FX CPU core
PDF  110 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB95F613K 데이터시트(HTML) 95 Page - Cypress Semiconductor

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Document Number: 002-04698 Rev. *A
Page 95 of 110
PRELIMINARY
MB95610H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Symbol
Pin
name
Condition
Value*2
Unit
Remarks
Min
Max
SCL clock “L”
width
tLOW
SCL
R = 1.7 k
,
C = 50 pF*1
(2
 nm/2)tMCLK  20
—
ns
Master mode
SCL clock “H”
width
tHIGH
SCL
(nm/2)tMCLK  20
(nm/2)tMCLK  20
ns
Master mode
START
condition hold
time
tHD;STA
SCL,
SDA
(-1
 nm/2)tMCLK  20
(-1
 nm)tMCLK  20
ns
Master mode
Maximum value is applied when
m, n = 1, 8.
Otherwise, the minimum value is
applied.
STOP condition
setup time
tSU;STO
SCL,
SDA
(1
 nm/2)tMCLK  20
(1
 nm/2)tMCLK  20
ns
Master mode
START
condition setup
time
tSU;STA
SCL,
SDA
(1
 nm/2)tMCLK  20
(1
 nm/2)tMCLK  20
ns
Master mode
Bus free time
between STOP
condition and
START
condition
tBUF
SCL,
SDA
(2 nm
 4) tMCLK  20
—
ns
Data hold time
tHD;DAT
SCL,
SDA
3 tMCLK  20
—
ns
Master mode
Data setup time
tSU;DAT
SCL,
SDA
(-2
 nm/2) tMCLK  20
(-1
 nm/2) tMCLK  20
ns
Master mode
It is assumed that “L” of SCL is
not extended. The minimum
value is applied to the first bit of
continuous data. Otherwise, the
maximum value is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL
(nm/2) tMCLK  20
(1
 nm/2) tMCLK  20
ns
The minimum value is applied to
the interrupt at the ninth SCL
.
The maximum value is applied to
the interrupt at the eighth SCL
.
SCL clock “L”
width
tLOW
SCL
4 tMCLK  20
—
ns
At reception
SCL clock “H”
width
tHIGH
SCL
4 tMCLK  20
—
ns
At reception
SDA
SCL
tWAKEUP
tHD;STA
tSU;DAT
fSCL
tHD;STA
tSU;STA
tLOW
tHD;DAT
tHIGH
tSU;STO
tBUF



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