MB91F467DA datasheet(26/137 Pages) CYPRESS

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Document Number: 002-04613 Rev. *A

Page 26 of 137

MB91460D Series

8. CPU and Control Unit

The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for

embedded applications.

8.1 Features

• Adoption of RISC architecture

Basic instruction: 1 instruction per cycle

• General-purpose registers: 32-bit × 16 registers

• 4 Gbytes linear memory space

• Multiplier installed

32-bit × 32-bit multiplication: 5 cycles

16-bit × 16-bit multiplication: 3 cycles

• Enhanced interrupt processing function

Quick response speed (6 cycles)

Multiple-interrupt support

Level mask function (16 levels)

• Enhanced instructions for I/O operation

Memory-to-memory transfer instruction

Bit processing instruction

Basic instruction word length: 16 bits

• Low-power consumption

Sleep mode/stop mode

8.2 Internal architecture

• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other.

• A 32-bit

 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources.

•A Harvard

 Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and

the bus controller.

MB91F467DA 데이터시트(PDF) 26 Page - Cypress Semiconductor