L5988D datasheet(34/52 Pages) STMICROELECTRONICS

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Application information

L5988D

34/52

DocID15324 Rev 4

The guidelines for positioning the poles and the zeroes and for calculating the component

values can be summarized as follow:

Choose a value for R8, usually between 1k and 5k, in order to have values of C5 and

C6 not comparable with parasitic capacitance of the board.

Choose a gain (R5/R8) in order to have the required bandwidth (BW), that means:

Equation 35

Where fESR is the ESR zero:

Equation 36

and VS is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin

constant.

Calculate C5 by placing the zero one decade below the output filter double pole:

Equation 37

Then calculate C7 in order to place the second pole at four times the system bandwidth

(BW):

Equation 38

For example with VOUT = 1.2V, VIN = 12 V, IO = 4 A, L = 4.7 H, COUT = 330 F,

ESR = 35 m

 the type II compensation network is:

Equation 39

fESR

fLC

------------





fESR

------------

VIN

--------- R8





fESR

 ESR C

OUT



--------------------------------------------

 R

5 fLC



-------------------------------

 R

5 C5 4BW



–



--------------------------------------------------------------

R8 4.7k

R6 4.7K

R5 22k

C5 2.2nF

C6 33pF





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