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STM32F411RET6 데이터시트(PDF) 126 Page - STMicroelectronics |
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STM32F411RET6 데이터시트(HTML) 126 Page - STMicroelectronics |
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126 / 149 page ![]() Package information STM32F411xC STM32F411xE 126/149 DocID026289 Rev 6 Device marking for WLCSP49 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 48. WLCSP49 marking (package top view) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. Table 80. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed |
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