SC16C752B datasheet(16/47 Pages) PHILIPS

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Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

16 of 47

9397 750 14443

6.6.2

Block DMA transfers (DMA mode 1)

Figure 11 shows TXRDY and RXRDY in DMA mode 1.

Transmitter: TXRDY is active when there is a trigger level number of spaces

available. It becomes inactive when the FIFO is full.

Receiver: RXRDY becomes active when the trigger level has been reached, or when

a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in

the RX FIFO is ﬂagged by LSR[7].

6.7 Sleep mode

Sleep mode is an enhanced feature of the SC16C752B UART. It is enabled when

EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is

entered when:

• The serial data input line, RX, is idle (see Section 6.8 “Break and time-out

conditions”).

• The TX FIFO and TX shift register are empty.

• There are no interrupts pending except THR and time-out interrupts.

Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In sleep mode, the UART clock and baud rate clock are stopped. Since most registers

are clocked using these clocks, the power consumption is greatly reduced. The UART

will wake up when any change is detected on the RX line, when there is any change

in the state of the modem input pins, or if data is written to the TX FIFO.

Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not

be done during sleep mode. Therefore, it is advisable to disable sleep mode using

IER[4] before writing to DLL or DLH.

Fig 11. TXRDY and RXRDY in DMA mode 1.

wrptr

TXRDY

FIFO full

TXRDY

rdptr

FIFO EMPTY

RXRDY

002aaa234

trigger

level

trigger

level

at least one

location filled

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