SC16C752B datasheet(24/47 Pages) PHILIPS

24 / 47 page

Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

24 of 47

9397 750 14443

7.5 Line status register (LSR)

Table 13 shows the line status register bit settings.

When the LSR is read, LSR[4:2] reﬂect the error bits (BI, FE, PE) of the character at

the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not

physically exist, as the data read from the RX FIFO is output directly onto the output

data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identiﬁed

by reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only

when there are no more errors remaining in the FIFO.

Reading the LSR does not cause an increment of the RX FIFO read pointer. The

RX FIFO read pointer is incremented by reading the RHR.

Table 13:

Line Status Register bits description

Bit

Symbol

Description

LSR[7]

FIFO data error.

Logic 0 = No error (normal default condition).

Logic 1 = At least one parity error, framing error, or break indication is

in the receiver FIFO. This bit is cleared when no more errors are

present in the FIFO.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator.

Logic 0 = Transmitter hold and shift registers are not empty.

Logic 1 = Transmitter hold and shift registers are empty.

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator.

Logic 0 = Transmit hold register is not empty.

Logic 1 = Transmit hold register is empty. The processor can now load

up to 64 bytes of data into the THR if the TX FIFO is enabled.

LSR[4]

Break interrupt.

Logic 0 = No break condition (normal default condition).

Logic1=A break condition occurred and associated byte is 00, i.e.,

RX was LOW for one character time frame.

LSR[3]

Framing error.

Logic 0 = No framing error in data being read from RX FIFO (normal

default condition).

Logic1=Framing error occurred in data being read from RX FIFO, i.e.,

received data did not have a valid stop bit.

LSR[2]

Parity error.

Logic 0 = No parity error (normal default condition).

Logic 1 = Parity error in data being read from RX FIFO.

LSR[1]

Overrun error.

Logic 0 = No overrun error (normal default condition).

Logic 1 = Overrun error has occurred.

LSR[0]

Data in receiver.

Logic 0 = No data in receive FIFO (normal default condition).

Logic 1 = At least one character in the RX FIFO.

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