SC16C752B datasheet(25/47 Pages) PHILIPS

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Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

25 of 47

9397 750 14443

Remark: The three error bits (parity, framing, break) may not be updated correctly in

the ﬁrst read of the LSR when the input clock (XTAL1) is running faster than 36 MHz.

However, the second read is always correct. It is strongly recommended that when

using this device with a clock faster than 36 MHz, that the LSR be read twice and only

the second read be used for decision making. All other bits in the LSR are correct on

all reads.

7.6 Modem control register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is

emulating the modem. Table 14 shows modem control register bit settings.

[1]

MCR[7:5] can only be modiﬁed when EFR[4] is set, i.e., EFR[4] is a write enable.

Table 14:

Modem Control Register bits description

Bit

Symbol

Description

MCR[7] [1]

Clock select.

Logic 0 = Divide-by-1 clock input.

Logic 1 = Divide-by-4 clock input.

MCR[6] [1]

TCR and TLR enable.

Logic 0 = no action.

Logic 1 = Enable access to the TCR and TLR registers.

MCR[5] [1]

Xon Any.

Logic 0 = Disable Xon Any function.

Logic 1 = Enable Xon Any function.

MCR[4]

Enable loop-back.

Logic 0 = Normal operating mode.

Logic 1 = Enable local loop-back mode (internal). In this mode the

MCR[3:0] signals are looped back into MSR[7:4] and the TX output

is looped back to the RX input internally.

MCR[3]

IRQ enable OP.

Logic0=Forces INTA-INTB outputs to the 3-State mode and OP

output to HIGH state.

Logic1=Forces the INTA-INTB outputs to the active state and OP

output to LOW state. In loop-back mode, controls MSR[7].

MCR[2]

FIFO Ready enable.

Logic 0 = Disable the FIFO Rdy register.

Logic 1 = Enable the FIFO Rdy register.

In loop-back mode, controls MSR[6].

MCR[1]

RTS

Logic 0 = Force RTS output to inactive (HIGH).

Logic 1 = Force RTS output to active (LOW).

In loop-back mode, controls MSR[4]. If Auto-RTS is enabled, the

RTS output is controlled by hardware ﬂow control.

MCR[0]

DTR

Logic 0 = Force DTR output to inactive (HIGH).

Logic 1 = Force DTR output to active (LOW).

In loop-back mode, controls MSR[5].

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