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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SC2200 데이터시트(PDF) 59 Page - National Semiconductor (TI) |
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SC2200 데이터시트(HTML) 59 Page - National Semiconductor (TI) |
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59 / 433 page  Revision 3.0 59 www.national.com Signal Definitions (Continued) SDCLK_OUT AH28 AK28 O SDRAM Clock Output. This output is routed back to SDCLK_IN. The board designer should vary the length of the board trace to control skew between SDCLK_IN and SDCLK. --- 2.4.3 Video Port Interface Signals Signal Name Ball No. Type Description Mux EBGA TEPBGA VPD7 AJ6 G31 I Video Port Data. The data is input from the CCIR-656 video decoder. --- VPD6 AJ7 H28 --- VPD5 AL6 H29 --- VPD4 AH8 H30 --- VPD3 AL7 H31 --- VPD2 AJ8 J28 --- VPD1 AK8 J29 --- VPD0 AH9 J30 --- VPCKIN AH7 F31 I Video Port Clock Input. The clock input from the video decoder. --- 2.4.4 CRT/TFT Interface Signals Signal Name Ball No. Type Description Mux EBGA TEPBGA DDC_SCL A20 Y1 O DDC Serial Clock. This is the serial clock for the VESA Display Data Channel interface. It is used for monitor communications. The DDC2B standard is supported by this inter- face. IDE_DATA10 DDC_SDA C20 Y2 I/O DDC Serial Data. This is the bidirectional serial data signal for the VESA Display Data Channel interface. It is used for monitor com- munications. The DDC2B standard is sup- ported by this interface. IDE_DATA9 HSYNC J1 A11 O Horizontal Sync --- VSYNC J2 B11 O Vertical Sync --- VREF P1 D16 I/O Voltage Reference. Reference voltage for CRT PLL and DAC. This signal reflects the internal voltage reference. If internal voltage reference is used (recommended), leave this ball disconnected. If an external voltage ref- erence is used, this input is tied to a 1.235V reference. --- 2.4.2 Memory Interface Signals (Continued) Signal Name Ball No. Type Description Mux EBGA TEPBGA |
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