SC2200 datasheet(65/433 Pages) NSC

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Signal Definitions (Continued)

SERR#

I/O

System Error. SERR# canbeassertedby

any agent for reporting errors other than PCI

parity, so that the PCI central agent notifies

the processor. When the Parity Enable bit is

set in the Memory Controller Configuration

of a parity error in read operations from

DRAM.

This signal is internally connected to a pull-

up resistor.

---

REQ1#

Request Lines. REQ[1:0]# indicate to the

arbiter that an agent requires the bus. Each

master has its own REQ# line. REQ# priori-

ties (in order) are:

VIP

IDE Channel 0

IDE Channel 1

Audio

USB

External REQ0#

External REQ1#.

Each REQ# is internally connected to a pull-

up resistor.

---

REQ0#

---

GNT1#

Grant Lines. GNT[1:0]# indicate to the

requesting master that it has been granted

access to the bus. Each master has its own

GNT# line. GNT# can be retracted at any

time ahigherREQ#isreceivedorif the mas-

ter does not begin a cycle within a minimum

period of time (16 PCI clocks).

Each of these signals is internally connected

to a pull-up resistor.

GNT0#must havea pull-upresistor of 1.5

Ω and GNT1# must have a pull-down resis-

tor of 1.5 K

Ω.

DID1 (Strap)

GNT0#

DID0 (Strap)

2.4.6

PCI Bus Interface Signals (Continued)

Signal Name

BalL No.

Type

Description

Mux

EBGA

TEPBGA

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