SC2200 datasheet(85/433 Pages) NSC

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General Configuration Block (Continued)

TRDESEL (Select TRDE#). Selects ball function.

Ball #

0: Sub-ISA Signal

1: GPIO Signal

EBGA / TEPBGA

Name

Add’l Dependencies

Name

Add’l Dependencies

H1 / D11

TRDE#

None

GPIO0

None

EIDE (Enable IDE Outputs). This bit enables IDE output signals.

0: IDE signals are HiZ. Other signals multiplexed on the same balls are HiZ until this bit is set. (without regard to bit 24 of

this register). This bit does not control IDE channel 1 control signals selected by bit 8 of this register.

1: Signals are enabled.

ETFT (Enable TFT Outputs). This bit enables TFT output signals, that are multiplexed with the Parallel Port and controlled

by PMR[23].

0: Signals TFTD[17:0], TFTDE and TFTDCK are set to 0.

1: Signals TFTD[17:0], TFTDE and TFTDCK are enabled.

Note:

TFTDCK that is multiplexed on IDE_RST# (EBGA ball A22 / TEPBGA ball AA1) is also enabled by this bit.

IOCHRDY (Select IOCHRDY). Selects ball function.

Ball #

0: PCI, GPIO Signal

1: Sub-ISA Signal

EBGA / TEPBGA

Name

Add’l Dependencies

Name

Add’l Dependencies

H4 / C9

GPIO19

PMR[4] = 0

IOCHRDY

PMR[4] = 1

INTC#

PMR[4] = 1

Undefined

PMR[4] = 0

IDE1SEL (Select IDE Channel 1). Selects IDE Channel 1 or GPIO ball functions. Works in conjunction with PMR[18] and

PMR[17], see PMR[18] and PMR[17] for definitions.

DOCCSSEL (Select DOCCS#). Selects DOCCS# or GPIO20 ball functions. Works in conjunction with PMR[23], see

PMR[23] for definition.

SP3SEL (Select UART3). Selects ball functions.

Ball #

0: IR Signals

1: Serial Port Signals

EBGA / TEPBGA

Name

Add’l Dependencies

Name

Add’l Dependencies

J28 / AK8

IRRX1

None

SIN3

None

J3 / C11

IRTX

None

SOUT3

None

IOCS0SEL (Select IOCS0#). Selects ball function. Works in conjunction with PMR[23], see PMR[23] for definition.

INTCSEL (Select INTC#). Selects ball function. Works in conjunction with PMR[9], see PMR[9] for definition.

Reserved. Write as read.

DOCWRSEL (Select DiskOnChip and NAND Flash Command Lines). Selects ball functions. Works in conjunction with

PMR[21], see PMR[21] for definition.

Reserved. Write as read.

PCBEEPSEL (Select PC_BEEP). Selects ball function.

Ball #

0:GPIO Signal

1:Audio Signal

EBGA / TEPBGA

Name

Add’l Dependencies

Name

Add’l Dependencies

AL15 / V31

GPIO16

FPCI_MON = 0

PC_BEEP

FPCI_MON] = 0

F_DEVSEL#

FPCI_MON = 1

F_DEVSEL#

FPCI_MON = 1

Offset 34h-37h

Miscellaneous Configuration Register - MCR (R/W)

Reset Value: 0000001h

Power-on reset value: The BOOT16 strap pin selects "Enable 16-Bit Wide Boot Memory".

DID0 (EBGA Ball D4 / TEPBGA Ball C5) Strap Status. (Read Only) Represents the value of the strap that is latched after

power-on reset. Read in conjunction with bit 29.

FPCI_MON (EBGA Ball D3 / TEPBGA Ball A4) Strap Status. (Read Only) Represents the value of the strap that is

latched after power-on reset. Indicates if Fast-PCI monitoring output signals (instead of Parallel Port and some audio sig-

nals) are enabled. The state of this bit along with PMR[27] control the Fast-PCI monitoring function. See PMR[27] definition.

DID1 (EBGA Ball D2 / TEPBGA Ball C6) Strap Status. (Read Only) Represents the value of the strap that is latched after

power-on reset. Read in conjunction with bit 31.

28:20

Reserved

19:18

Reserved. Write as 0.

HSYNC Timing. HSYNC timing control for TFT.

0: HSYNC timing suited for CRT.

1: HSYNC timing suited for TFT.

Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)

Bit

Description

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