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PC87309VLJ 데이터시트(PDF) 174 Page - National Semiconductor (TI) |
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PC87309VLJ 데이터시트(HTML) 174 Page - National Semiconductor (TI) |
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174 / 192 page ![]() Device Specifications 174 www.national.com Read After Write Operation to All Registers and RAM 10.3.4 Baud Output Timing 1. Not tested. Guaranteed by design. A11-0 D7-0 AEN WR (Input) tWRR or CS RD Symbol Parameter Conditions Min Max Unit N Baud Divisor 1 65535 nsec tBHD Baud Output Positive Edge Delay1 CLK = 24 MHz/2, 100 pF load 56 nsec tBLD Baud Output Negative Edge Delay1 CLK = 24 MHz/2, 100 pF load 56 nsec CLK BAUD OUT (÷1) BAUD OUT ( ÷2) BAUD OUT ( ÷3) BAUD OUT ( ÷N, N > 3) tBLD tBLD tBLD tBLD tBHD tBHD tBHD N tBHD |
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