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PC97307 데이터시트(PDF) 203 Page - National Semiconductor (TI) |
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PC97307 데이터시트(HTML) 203 Page - National Semiconductor (TI) |
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203 / 218 page ![]() 203 Device Description www.national.com TABLE 13-46. ECP DMA Timing FIGURE 13-16. ECP DMA Timing a. One DMA transaction takes six clock cycles. b. tCP is defined in Table 13-35. c. Only in case of pending DRQ. d. The active edge of RD or WR and TC is recognized only when DACK is active. Symbol Parameter Min Max Unit tKIP DACK Inactive Pulse Width 25 nsec tKKP DACK Active Pulse Width 65 nsec tKQP DACK Active Edge to DRQ Inactive ab 65 + (6 x 32 x tCP) nsec tQKP DRQ to DACK Active Edge 10 nsec tQPP DRQ Period 330 nsec tQQP DRQ Inactive Non-Burst Pulse Width 300 400 c nsec tQRP DRQ to RD, WR Active 15 nsec tRQP RD, WR Active Edge to DRQ Inactive d 65 nsec tTQP TC Active Edge to DRQ Inactive 75 nsec tTT TC Active Pulse Width 50 nsec tQKP tKQP tQPP tTT tKKP tQRP tQQP tKIP tRQP tTQP DRQ DACK RD, WR TC |
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