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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC97307 데이터시트(PDF) 204 Page - National Semiconductor (TI) |
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PC97307 데이터시트(HTML) 204 Page - National Semiconductor (TI) |
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204 / 218 page  204 Device Description www.national.com 13.3.12 Reset Timing TABLE 13-47. Reset Timing Note: In PC-AT mode, the DRQ and IRQ signals of the FDC are in TRI-STATE after time tSRC. FIGURE 13-17. Reset Timing 13.3.13 Write Data Timing TABLE 13-48. Write Data Timing TABLE 13-49. Write Data Timing – Minimum tWDW Values FIGURE 13-18. Write Data Timing a. The software reset pulse width is 100 nsec. b. Not tested. Guaranteed by design. a. Not tested. Guaranteed by design. a. tICP is the internal clock period defined in Table 13-36. Symbol Parameter Min Max Unit tRW Reset Width a 100 µsec tSRC Reset to Control Inactive b 300 nsec Symbol Parameter Min Max Unit tHDH HDSEL Hold from WGATE Inactivea 750 µsec tHDS HDSEL Setup to WGATE Activea 100 µsec tWDW Write Data Pulse Width Table 13-49 Data Rate tDRP tWDW tWDW Value Unit 1 Mbps 1000 2 x tICP a 250 nsec 500 Kbps 2000 2 x tICP a 250 nsec 300 Kbps 3333 2 x tICP a 375 nsec 250 Kbps 4000 2 x tICP a 500 nsec tRW tSRC MR DRQ, INT, WGATE (Note) tHDS tHDH tWDW HDSEL WGATE WDATA |
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