PC97338VLJ datasheet(36/221 Pages) NSC

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2.0 Configuration

2.1

OVERVIEW

The configuration register set consists of 37 registers,

which control the Chip set-up. Setup values stored in

these registers enable or disable major functions,

such as FDC, SCCs and the parallel port, and set

functional parameters such as functional mode selec-

tion, pin functionality, interrupt configuration, hard-

ware-controlled power down options and I/O address

assignment.

Table 7 lists these registers, their mnemonic abbrevi-

ations and index number (which serves as an address

offset). Bitmaps of these registers, in order of increas-

ing index numbers, appear in Section 2.3.1 on page

41.

2.2

CONFIGURATION REGISTER

SETUP

Certain configuration registers are setup by hardware

pin strapping schemes. All others are setup by soft-

ware. The hardware-configured registers may be up-

dated by software after power-up.

2.2.1

Hardware Device Configuration

Three configuration registers in the Chip are setup by

hardware pin strapping options. The FER, FAR and

PTR register default contents are setup by CFG0 dur-

ing reset.

CFG0 is set to 0 level by default, and may be changed

to logical 1 by attaching an external pull-up resistor.

The values set by this method are loaded into the de-

vice registers during reset. The setting of this pin se-

lects one of two sets of default values for loading. This

enables automatic configuration without software in-

tervention.

Table 6 shows the hardware-controlled default config-

urations.

CFG0 controls selection of 11 address bits with fully

standard interface of SCC2, or 16 address bits and

SCC2 with SIN and SOUT signals only.

• 11-bit address mode - The chip is in this mode, if

during reset CFG0 = 1. SCC2 wakes up with the

full standard interface.

• 16-bit address mode - The chip is in this mode, if

during reset CFG0 = 0. SCC2 wakes up in 16550

UART/SIR mode.

The default configuration can be modified by software

at any time after reset by using the access procedure

described in the Section 2.2.

TABLE 6. Default Configurations Controlled by Hardware

CFG0

Reset Value of FAR, FER, PTR

Reset Configuration

0(Default)

FER = xx000000B

PTR = 00x000x0B

FAR = 00010000B

• All modules disabled (power down)

• 16 address bits.

• SCC2 in Legacy SIR mode, with SIN and SOUT signals

only.

• All modules disabled (power down).

• 11 address bits.

• SCC2 in Legacy mode, with the full standard interface.

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