| 전자부품 데이터시트 검색엔진 |
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PC97338VLJ 데이터시트(PDF) 67 Page - National Semiconductor (TI) |
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PC97338VLJ 데이터시트(HTML) 67 Page - National Semiconductor (TI) |
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67 / 221 page ![]() 67 www.national.com Bits 2-0 - SCC2 Receiver Channel Selection Upon reset these bits are initialized to 000. It is the software’s responsibility to route all DMA sources onto the ISA DMA channels correctly. Table 33 shows the encoding options for these bits. TABLE 33. SCC2 Receiver Channel Selection Bits 5-3 - SCC2 Transmission Channel Selection Upon reset these bits are initialized to 000. It is the software’s responsibility to route all DMA sources onto the ISA DMA channels correctly. Table 34 shows the encoding options for these bits. TABLE 34. SCC2 Transmission Channel Selec- tion 2.3.37 SuperI/O Configuration 3 Register (SCF3), Index 50h This register controls the following. Upon reset, all im- plemented bits are initialized to 0. FIGURE 39. SCF3 Register Bitmap Bit 2 Bit 1 Bit 0 SCC2 Receiver Channel Selection Settings 0 0 0 Disabled. SCC2 DMA is not connected to any ISA DMA channel, i.e., it is not connected to any of the chip’s DMA pins. 0 0 1 SCC2 receiver DMA request and acknowledge signals are connected to DRQ0 and DACK0 pins. 0 1 0 SCC2 receiver DMA request and acknowledge signals are connected to DRQ1 and DACK1 pins. 0 1 1 SCC2 receiver DMA request and acknowledge signals are connected to DRQ2 and DACK2 pins. 1 0 0 SCC2 receiver DMA request and acknowledge signals are connected to DRQ3 and DACK3 pins. 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Bit 5 Bit 4 Bit 3 SCC2 Transmission Channel Selection Setting 0 0 0 Disabled. SCC2 DMA is not connected to any ISA DMA channel, i.e., it is not connected to any of the chip’s DMA pins. 0 0 1 SCC2 transmitter DMA request and acknowledge signals are connected to DRQ0 and DACK0 pins. 0 1 0 SCC2 transmitter DMA request and acknowledge signals are connected to DRQ1 and DACK1 pins. 0 1 1 SCC2 transmitter DMA request and acknowledge signals are connected to DRQ2 and DACK2 pins. 1 0 0 SCC2 transmitter DMA request and acknowledge signals are connected to DRQ3 and DACK3 pins. 101 Reserved 110 Reserved 111 Reserved 76 543 21 0 Register 3 (SCF3) Reset Required Index 50h 0 0 0 0 0 0 SuperI/O Configuration Select DRATE, MSEN1, Select DRV2, PNF, DR23, Select IRQI2, IRRX2 or IRSL0/ID0 Select MTR1, IDLE or IRSL2/ID2 CS0, SIRQI2 or DACK3 SIRQI3 or IRSL2 Reserved Reserved Reserved Reserved |
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