PC97338VLJ datasheet(51/221 Pages) NSC

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Bit 4 - PD and IDLE or IRSL2/

ID2 Enable

This is the PD and IDLE (FDC power management

output signals) or IRSL2/

ID2 enable bit. When bit

2 of the SCF3 register is 1, IRSL2 controls pin 43

(PQFP) or 41 (TQFP) instead of MTR1 or IDLE.

See Tables 16 and 17.

ID2 is available only in

PC97338.

0 - MTR1 or IRSL2/

ID2 controls pin 43 (PQFP) or

41 (TQFP), and DR1 controls pin 45 (PQFP)

or 43 (TQFP).

1 - IDLE or IRSL2/

ID2 controls pin 43 (PQFP) or

41 (TQFP), and PD controls pin 45 (PQFP) or

43 (TQFP).

TABLE 16. Bit Settings to Enable MRT1, IDLE or

IRSL2

TABLE 17. Bit Settings to Enable DR1 or PD

Bit 5 - Selective Lock

This bit enables locking of the following configura-

tion bits: bit 5 of PMC (this bit), bit 4 of FER, bits 7

through 0 of FAR, bit 3 of PTR and bit 6 of FCR.

Unlike bit 6 of PTR, it does not lock all the config-

uration bits.

Once this bit is set by software it can only be

cleared by a hardware reset. This bit should be

used instead of bit 6 of PTR if a configuration bit

should be dynamically modified by software (like

PMC bits).

0 - No lock, except via bit 6 of PTR.

1 - Any write to the above configuration bits is ig-

nored, until a Master Reset clears this bit.

Bit 6 - Parallel Port (PPM) TRI-STATE Enable

This bit enables reduction in power consumption,

when the SuperI/O chip is in power-down mode, or

the parallel port is disabled, by placing the PPM

output signals in TRI-STATE, and blocking the

PPM input signals.

0 - The parallel port pins are enabled.

1 - If the parallel port is disabled, or the Super I/O

chip is in power-down mode, the output sig-

nals of the parallel port, pins (except the Par-

allel Port-allocated interrupt line]) are in TRI-

STATE, and the input signals are blocked to

reduce their leakage currents.

The values of the blocked input signals are:

BUSY=1,

PE=0,

SLCT=0,

ACK=1

and

ERR=1.

Bit 7 - Reserved

This bit is reserved. To maintain compatibility with

future SIO chips, do not modify this bit when this

preserve the value of this bit.

2.3.8

Tape, SCCs and Parallel Port

Configuration Register (TUP),

Index 07h

The TUP Register is cleared to 0XX00000 on reset.

FIGURE 9. TUP Register Bitmap

Bit 0 - Reserved

This bit is reserved.

Bit 1 - FDC 2 Mbps Enable

Upon reset, this bit is cleared to 0.

0 - 2 Mbps is not supported by the FDC, and the

FDC clock is 24 MHz. (Default)

1 - 2 Mbps is supported by the FDC, and the

FDC clock is 48 MHz The operating voltage

should be 5 V. See Section 3.1.

Bit 2 - EPP Time-Out Interrupt Enable

0 - The EPP time-out interrupt is masked.

1 - The EPP time-out interrupt is generated on

the selected IRQ line (the Parallel Port-allo-

cated interrupt line), according to bit 6 of PCR.

Bit 2 of

SCF3

Bit 4 of

PMC

Function Selected on Pin #43

(PQFP) or Pin #41 (TQFP)

MTR1

IDLE

IRSL2

Bit 4 of

PMC

Function Selected on Pin #45

(PQFP) or Pin #43 (TQFP)

DR1

1PD

321

(TUP)

Reset

Required

Tape, SCCs and Parallel Port

Index 07h

Configuration Register

Reserved

FDC 2 Mbps Enable

EPP Time-out Interrupt Enable

Reserved(PC97338)/MIDI(PC87338)

Reserved

IDLE Status

PD Status

IDLE Pin Mask

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