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PC97338VLJ 데이터시트(PDF) 137 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 PC97338VLJ
상세설명  ACPI 1.0 and PC98/99 Compliant SuperI/O
PDF  221 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

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4.4.6
ECP Address FIFO (AFIFO)
Register, Bits 7-5 of ECR = 011,
Offset 000h
The ECP Address FIFO Register (AFIFO) is write
only. In the forward direction (bit 5 of DCR is 0) a byte
written into this register is pushed into the FIFO and
tagged as a command.
Reading this register returns undefined contents. Writ-
ing to this register in a backward direction (bit 5 of DCR
is 1) has no effect and the data is ignored.
FIGURE 78. AFIFO Register Bitmap
4.4.7
ECP Status Register (DSR),
Offset 001h
This read-only register displays device status. Writes
to this DSR have no effect and the data is ignored.
This register should not be confused with the DSR
register of the Floppy Disk Controller (FDC).
FIGURE 79. ECP DSR Register Bitmap
Bits 0 - 2 - Reserved
These bits are reserved and are always 1.
Bit 3 - ERR Status
This bit reflects the status of the ERR signal.
0 - Printer error
1 - No printer error
Bit 4 - SLCT Status
This bit reflects the status of the Select signal. The
printer sets this signal high when it is online and
selected
0 - Printer not selected (default)
1 - Printer selected and online
Bit 5 - PE Status
This bit reflects the status of the Paper End (PE)
signal.
0 - Paper not ended
1 - NO paper in printer.
Bit 6 - ACK Status
This bit reflects the status of the ACK signal. This
signal is pulsed low after a character is received.
0 - Character received.
1 - No character received (Default)
Bit 7 -Printer Status
This bit reflects the inverse of the state of the
BUSY signal.
0 - Printer is busy (cannot accept another charac-
ter now)
1 - Printer not busy - ready for another character.
4.4.8
ECP Control Register (DCR),
Offset 002h
Reading this register returns the register content (not
the pin values, as in SPP mode).
FIGURE 80. DCR Register Bitmap
76
54
321
0
Reset
Required
0
0
0
0
0
0
0
0
ECP Address Register
(AFIFO)
Offset 000h
A2
A4
A5
A6
A7
A0
A1
A3
Bits 7-5 of ECR = 011
76
54
321
0
Reset
Required
1
1
1
1
1
1
ECP Status Register
(DSR)
Offset 001h
Reserved
SLCT Status
PE Status
ACK Status
Printer Status
Reserved
Reserved
ERR Status
All ECP Modes
76
54
321
0
Reset
Required
0
0
0
0
0
0
1
1
ECP Control
Register (DCR)
Offset 002h
Printer Initialization Control(INIT)
Interrupt Enable
Direction Control
Reserved
Reserved
Data Strobe Control
Automatic Line Feed Control
Parallel Port Input Control
All ECP Modes



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