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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC97338VLJ 데이터시트(PDF) 174 Page - National Semiconductor (TI) |
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PC97338VLJ 데이터시트(HTML) 174 Page - National Semiconductor (TI) |
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174 / 221 page  174 www.national.com B3-0 MPW [3–0] – MIR Signal Pulse Width TABLE 89. MIR Pulse Width Settings B7-4 Reserved. Write 0's. 5.20.3 SIR_PW – SIR Pulse Width Register This register determines the width of the transmitted SIR infrared pulses. The programmed value has no effect on the SIR re- ceiver. After reset, the content of this register is 0. FIGURE 88. SIR Pulse Width Register 5.20.4 LCR/BSR – Link Control/Bank Select Registers These registers are the same as in bank 0. 5.20.5 BFPL – Beginning Flags/Preamble Length Register Used to program the number of beginning flags and preamble symbols for MIR and FIR modes respec- tively. After reset, the content of this register is 2Ah, select- ing 2 beginning flags and 16 preamble symbols. FIGURE 88. Beginning Flags/Preamble Length Register TABLE 90. FIR Preamble Length ENCODING Pulse Width MDRS = 0 Pulse Width MDRS = 1 00XX Reserved Reserved 0100 83.33 ns 166.66 ns 0101 104.16 ns 208.33 ns 0110 125 ns 250 ns 0111 145.83 ns 291.66 ns 1000 166.66 ns 333.33 ns 1001 187.50 ns 374.99 ns 1010 208.33 ns 416.66 ns 1011 229.16 ns 458.33 1100 250 ns 500 ns 1101 270.83 ns 541.66 ns 1110 291.66 ns 583.32 ns 1111 312.5 ns 625 ns B3-0 SPW [3-0] – SIR Signal Pulse Width. Encoding Pulse Width 0000 3/16 of bit time 1101 1.6 µs Other encodings are reserved and will select a pulse width of 1.6 µs. B7-4 Reserved. Write 0's. 7 654 321 0 Reset Required 0 0 0 0 0 0 0 0 0 0 0 0 SPW(3-0) Reserved B3–0 FPL [3–0] – FIR Preamble Length. Selects the number of preamble symbols for FIR frames. ENCODING Preamble Length 0000 Reserved 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 8 1000 10 1001 12 1010 16 (Default) 1011 20 1100 24 1101 28 1110 32 1111 Reserved B7–4 MBF [3–0] – MIR Beginning Flags. Selects the number of beginning flags for MIR frames. 7 6 5 432 10 Reset Required 0 1 0 1 0 1 0 0 FPL(3-0) MBF(7-4) |
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