PC87366 datasheet(127/240 Pages) NSC

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5.0 Fan Speed Monitor (Continued)

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Figure 16. Fan Speed Monitor

5.3

FAN SPEED MONITOR REGISTERS

The FMSPR register is used to hold the current speed reading (which is represented by the latest NCBTP and refreshed

upon every FANIN pulse).

The FMTHR register holds the maximum allowed NCBTP value (representing the slowest speed at which the fan is allowed

to operate) without causing system alert.

Additional control and status bits are available through the FMCSR register. These include:

• Over Threshold. A status bit that indicates that the NCBTP has exceeded the threshold (the speed has dropped below

the allowed minimum).

• Overflow. A status bit that indicates that the NCBTP is higher than FFh. With a proper input clock selection, this means

that the speed is inefficiently low and is considered stopped.

• Speed Ready. A status bit that indicates that new, valid data has been loaded into the FMSPR register.

• Clock Select. A 2-bit control field that selects the counter clock rate as either 2 KHz, 4 KHz, 8 KHz or 16 KHz.

The following abbreviations are used to indicate the Register Type:

• R/W = Read/Write

• R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

• W=Write

• RO = Read Only

• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

5.3.1

Fan Speed Monitor Register Map

Offset

Mnemonic

Type

Section

Device specificNote 1.

Note 1. The location of this register is deﬁned in the

Device Architecture and Conﬁguration chapter.

FMTHR

Fan Monitor Threshold

R/W

5.3.2

Device specificNote 1.

FMSPR

Fan Monitor Speed

5.3.3

Device specificNote 1.

FMCSR

Fan Monitor Control and Status

Varies per bit

5.3.4

FMSPR Register

Clock Select

FANIN

Filter

(FMCSR, Bit 4)

Pos. Edge

Detector

Overﬂow

(FMCSR, Bit 2)

Up Counter

16 Khz

8 Khz

4 Khz

2 Khz

FMTHR Register

Comparator

Over

(FMCSR, Bit 1)

Threshold

Clear

Load

Interrupt Enable

(FMCSR, Bit 3)

Interrupt

(FMCSR, Bits 6-5)

Filter Disable

(FMCSR, Bit 0)

Speed Ready

Set

Clock

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