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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC87366 데이터시트(PDF) 178 Page - National Semiconductor (TI) |
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PC87366 데이터시트(HTML) 178 Page - National Semiconductor (TI) |
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178 / 240 page  11.0 Voltage Level Monitor (VLM) (Continued) 178 www.national.com Figure 35. VLM Functional Diagram 11.2.1 Voltage Measurement, Channels 0 through 10 Voltage is measured relative to 2.45*VREF.(VREF is the voltage of the VREF input, or the internal reference voltage.) The results are output to the Read Channel Voltage (RDCHV) register associated with the channel. The voltage measured is: Vi = 2.45*VREF *RDCHVi / 256 VSB,VDD and AVDD are internally divided by two. Therefore, the readouts are half their actual values. When external dividers are used to scale input voltage to within the dynamic range of the A/D Converter, appropriate scale factors should be taken into account. VHIGH and VLOW Limits, ALARM Output, IRQ and SMI The voltage reading is compared to two limits: VHIGH and VLOW. If the voltage reading is outside any of these limits, the respective status bit (Channel High Limit Exceeded or Channel Low Limit Exceeded) in the VCHCFST register is set. The status bit stays active until it is cleared by the software. An ALARM status bit in the VEVSTS0 or VEVSTS1 register is set when the Channel High Limit Exceeded or the Channel Low Limit Exceeded bit for the respective channel is set. SIB A/D Converter 14:1 Analog AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 MUX VLM Clock Divider Clock VIN0 AVI0 Control Logic Status, Data & Config Registers A/D AVI6 VIN0 VIN6 AD8 AD12 AD11 AD13 VSB VDD AD9 VBAT TS1 TS2 TS3 Low + High + Delay Start AVss IRQ ALARM SMI IRQ ALERT SMI Converter Analog Power 3.3 V VREF REF Internal VREF AVDD *2.45 AD10 AVDD VSB Power Overtemp + OTS } } To VLM Config To TMS Config |
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