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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC87366 데이터시트(PDF) 184 Page - National Semiconductor (TI) |
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PC87366 데이터시트(HTML) 184 Page - National Semiconductor (TI) |
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184 / 240 page  11.0 Voltage Level Monitor (VLM) (Continued) 184 www.national.com 11.5.4 Voltage Event to SMI Register 0 (VEVSMI0) This register is one of two registers that controls event routing to SMI. Location: Offset 02h Type: R/W 2 AVDD ALARM Event Status. This channel measures the internal AVDD power, using AVDD/2. 0: Voltage level within limits (default) 1: High or low limit exceeded 1 VBAT ALARM Event Status. This channel measures the VBAT power input. 0: Voltage level within limits (default) 1: High or low limit exceeded 0 VDD ALARM Event Status. This channel measures the internal VDD power, using VDD/2. 0: Voltage level within limits (default) 1: High or low limit exceeded Bit 76543210 Name VSB Event to SMI Enable AVI6 Event to SMI Enable AVI5 Event to SMI Enable AVI4 Event to SMI Enable AVI3 Event to SMI Enable AVI2 Event to SMI Enable AVI1 Event to SMI Enable AVI0 Event to SMI Enable Reset 00000000 Bit Description 7 VSB Event to SMI Enable 0: Disabled (default) 1: Enabled 6-0 AVI6-0 Event to SMI Enable 0: Disabled (default) 1: Enabled Bit Description |
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