STV2050A datasheet(30/83 Pages) STMICROELECTRONICS

부품명	STV2050A

상세설명	AUTOMATIC MULTISCAN DIGITAL CONVERGENCE PROCESSOR

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제조업체	STMICROELECTRONICS [STMicroelectronics]

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STV2050A - MASTER I²C BUS INTERFACE

– STX[0] =´EEPROM PROBLEM´

If A Read or Write sequence has been terminated with an access error, the STX[0] bit is set

to low. It is set back to high when the master starts the next R/W sequence.

6.6 DATA TRANSFER BETWEEN RAM AND EEPROM

Data is transfered using the following I²C BUS sequence after a bit in the E9 register has been

read or written: S DW SA D0 D1 D2 P

Where:

– SA = E9: Selection of the E9 register, EEPROMadd[2:0] is the hardware EEPROM address

used by the I²C Master,

– RWM[2:0] selects the Read or Write mode as previously described,

– HAM[2:0]: Hamming code used to protect the D0[7:0] and D1[7:4] data bits. Refer to Section

14.2 "HAMMING ENCODING" on page 62.

The total transfer lasts approximately 200 ms if the I²C master clock is operating at 70 kHz.

MSB

LSB

BYTE D0

BYTE D1

BYTE D2

ADD

EEPRO-

Madd [2:0]

XXX

ADS[

1:0]

RWM [2:0]

HAM[3:0]

STX[3:0]

STV2050A 데이터시트(PDF) 30 Page - STMicroelectronics