TNETV6446AINZWT datasheet(180/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

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6.14.1

Host-Port Interface (HPI) Electrical Data/Timing

Table 6-68. Timing Requirements for Host-Port Interface Cycles(1) (2) (see Figure 6-56 through

Figure 6-57)

A-513,

-594,

NO.

UNIT

-810

MIN

MAX

tsu(SELV-HSTBL)

Setup time, select signals(3) valid before HSTROBE low

th(HSTBL-SELV)

Hold time, select signals(3) valid after HSTROBE low

tw(HSTBL)

Pulse duration, HSTROBE low

tw(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

tsu(HDV-HSTBH)

Setup time, host data valid before HSTROBE high

th(HSTBH-HDV)

Hold time, host data valid after HSTROBE high

Hold time, HSTROBE high after HRDY low. HSTROBE should not be

th(HRDYL-HSTBH)

inactivated until HRDY is active (low); otherwise, HPI writes will not complete

properly.

(1)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2)

P = 1/CPU clock frequency in ns. For example, when running parts at 594 MHz, use P = 1.68 ns; when running parts at 810 MHz, use

P = 1.23 ns.

(3)

Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

Table 6-69. Switching Characteristics Over Recommended Operating Conditions During Host-Port

Interface Cycles(1) (see Figure 6-56 through Figure 6-57)

A-513,

-594,

NO.

PARAMETER

UNIT

-810

MIN

MAX

td(HSTBL-HRDYH)

Delay time, HSTROBE low to HRDY high(2)

td(HSTBL-HDLZ)

Delay time, HSTROBE low to HD low impedance for an HPI read

td(HDV-HRDYL)

Delay time, HD valid to HRDY low

toh(HSTBH-HDV)

Output hold time, HD valid after HSTROBE high

1.5

td(HSTBH-HDHZ)

Delay time, HSTROBE high to HD high impedance

Delay time, HSTROBE low to HD valid

td(HSTBL-HDV)

(HPI16 mode, 2nd half-word only)

td(HCSL-HRDYH)

Delay time, HCS low to HRDY high

(1)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2)

This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling

edge of HSTROBE, the HPI sends the request to the EDMA3 internal address generation hardware, and HRDY remains high until the

EDMA3 internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer

is full.

180

Peripheral and Electrical Specifications

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