TNETV6446AINZWT datasheet(177/227 Pages) TI1

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VCLK

(Positive Edge

Clocking)

VCLK

(Negative Edge

Clocking)

VCTL(B)

VDATA(C)

VCLKIN(A)

A. VCLKIN = PCLK or VPBECLK

B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE

C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]

TMS320DM6446

www.ti.com

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

Table 6-63. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to VCLK(1) (2) (see Figure 6-53)

A-513,

-594,

NO.

PARAMETER

MODE(3)

UNIT

-810

MIN

MAX

tc(VCLK)

Cycle time, VCLK

13.33

160

Pulse duration, VCLK high (positive-edge clocking)

H - 1.3(4)

H - 0.3(4)

tw(VCLKH)

Pulse duration, VCLK high (negative-edge clocking)

L - 1.3(4)

L - 0.3(4)

Pulse duration, VCLK low (positive-edge clocking)

L + 0.3(4)

L + 1.3(4)

tw(VCLKL)

Pulse duration, VCLK low (negative-edge clocking)

H + 0.3(4) H + 1.3(4)

tt(VCLK)

Transition time, VCLK

td(VCLKINH-VCLKH)

Delay time, VCLKIN high to VCLK high

td(VCLKINL-VCLKL)

Delay time, VCLKIN low to VCLK low

Delay time, VCLK negative edge to VCTL valid

7.5

td(VCLK-VCTLV)

Delay time, VCLK positive edge to VCTL valid

6.9

Delay time, VCLK negative edge to VCTL invalid

td(VCLKL-VCTLIV)

Delay time, VCLK positive edge to VCTL invalid

1.5

Delay time, VCLK negative edge to VDATA valid

6.8

td(VCLK-VDATAV)

Delay time, VCLK positive edge to VDATA valid

6.3

RGB

2.1

Delay time, VCLK negative edge to VDATA invalid

YCC

2.5

td(VCLKL-VDATAIV)

RGB

1.9

Delay time, VCLK positive edge to VDATA invalid

YCC

2.1

(1)

The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the

rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.

(2)

VCLKIN = PCLK or VPBECLK

(3)

RGB and YCC modes utilize different data pins. RGB mode uses data pins: R[7:0], G[7:0], and B[7:0]. YCC mode uses data pins:

COUT[7:0] and YOUT[7:0].

(4)

H and L are the high and low pulse widths of the input clock to the VPBE, respectively. For example, if VPBECLK is used as the input

clock and it has a high pulse duration of 6.67 ns, the resulting high pulse duration of VCLK, if positive-edge clocking is selected, will be a

MAX of 6.37 ns and a MIN of 5.27 ns.

Figure 6-53. VPBE Control and Data Output Timing With Respect to VCLK

Peripheral and Electrical Specifications

177

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