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TNETV6446AINZWT 데이터시트(PDF) 195 Page - Texas Instruments |
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TNETV6446AINZWT 데이터시트(HTML) 195 Page - Texas Instruments |
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195 / 227 page ![]() SPIx_CLK (Clock Polarity = 0) 1 2 3 SPIx_CLK (Clock Polarity = 1) TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 6.17.2 SPI Electrical Data/Timing Table 6-79. Timing Requirements for SPI (All Modes)(1) (see Figure 6-62) A-513, -594, NO. UNIT -810 MIN MAX 1 tc(CLK) Cycle time, SPI_CLK 30.3 56888.89 ns 2 tw(CLKH) Pulse duration, SPI_CLK high (All Master Modes) 0.45*T 0.55*T ns 3 tw(CLKL) Pulse duration, SPI_CLK low (All Master Modes 0.45*T 0.55*T ns (1) T = tc(CLK) [SPI_CLK period is equal to the SPI module clock divided by a configurable divider.] Figure 6-62. SPI_CLK Timing Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 195 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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