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TNETV6446AINZWT 데이터시트(PDF) 199 Page - Texas Instruments

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부품명 TNETV6446AINZWT
상세설명  Digital Media System-on-Chip
PDF  227 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV6446AINZWT 데이터시트(HTML) 199 Page - Texas Instruments

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10
8
4
3
7
12
5
6
14
2
3
13
Stop
Start
Repeated
Start
Stop
SDA
SCL
1
11
9
TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
6.18.2
I2C Electrical Data/Timing
6.18.2.1
Inter-Integrated Circuits (I2C) Timing
Table 6-85. Timing Requirements for I2C Timings(1) (see Figure 6-65)
A-513,
-594,
-810
NO.
UNIT
STANDARD
FAST MODE
MODE
MIN
MAX
MIN
MAX
1
tc(SCL)
Cycle time, SCL
10
2.5
µs
Setup time, SCL high before SDA low
2
tsu(SCLH-SDAL)
4.7
0.6
µs
(for a repeated START condition)
Hold time, SCL low after SDA low
3
th(SCLL-SDAL)
4
0.6
µs
(for a START and a repeated START condition)
4
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100(2)
ns
7
th(SDA-SCLL)
Hold time, SDA valid after SCL low
0(3)
0(3)
0.9(4)
µs
Pulse duration, SDA high between STOP and START
8
tw(SDAH)
4.7
1.3
µs
conditions
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
(5)
300
ns
10
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
(5)
300
ns
11
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
(5)
300
ns
12
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb
(5)
300
ns
Setup time, SCL high before SDA high (for STOP
13
tsu(SCLH-SDAH)
4
0.6
µs
condition)
14
tw(SP)
Pulse duration, spike (must be suppressed)
0
50
ns
15
Cb
(5)
Capacitive load for each bus line
400
400
pF
(1)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2)
A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3)
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4)
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5)
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 6-65. I2C Receive Timings
Copyright © 2005–2010, Texas Instruments Incorporated
Peripheral and Electrical Specifications
199
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