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LDF 데이터시트(PDF) 4 Page - STMicroelectronics |
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LDF 데이터시트(HTML) 4 Page - STMicroelectronics |
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4 / 33 page ![]() Pin configuration LDF 4/33 DocID025502 Rev 2 2 Pin configuration Figure 2: Pin connection (top view) Table 1: DPAK, PPAK pin description Pin n° Symbol Function PPAK DPAK 5 - ADJ/PG For adjustable versions: error amplifier input pin For fixed versions: power-good output 2 1 VIN Input voltage 4 3 VOUT Output voltage 1 - EN Enable pin logic input: low = shutdown, high = active 3 2 GND Ground TAB TAB GND Ground Table 2: DFN6-2x2 and 3x3 pin description Pin n° Symbol Function 2 ADJ/NC For adjustable versions: error amplifier input pin For fixed versions: not connected 6 VIN Input voltage 1 VOUT Output voltage 5 EN Enable pin logic input: low = shutdown, high = active 3 PG Power-good output 4 GND Ground Exposed pad GND Ground |
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