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SPC560P34L1 데이터시트(PDF) 69 Page - STMicroelectronics |
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SPC560P34L1 데이터시트(HTML) 69 Page - STMicroelectronics |
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69 / 103 page ![]() SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics Doc ID 16100 Rev 7 69/103 3.14.1 Input impedance and ADC accuracy To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high- impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS and CP2 being substantially two switched capacitances, with a frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS+CP2 equal to 3 pF, a resistance of 330 k Ω is obtained (REQ = 1 / (fc × (CS+CP2)), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS+CP2) and the sum of RS + RF, the external circuit must be designed to respect the Equation 4: Equation 4 Equation 4 generates a constraint for external network design, in particular on resistive path. V A R S R F + R EQ --------------------- • 1 2 ---LSB < |
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