SPC560P34L1 datasheet(73/103 Pages) STMICROELECTRONICS

73 / 103 page

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Electrical characteristics

Doc ID 16100 Rev 7

73/103

3.14.2

ADC conversion characteristics

Table 30.

ADC conversion characteristics

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

fCK

—

ADC clock frequency (depends on

ADC configuration)

(The duty cycle depends on ADC

clock(2) frequency)

—3(3)

—60

MHz

— Sampling frequency

—

1.53

MHz

— D Sampling time(4)

fADC = 20 MHz, INPSAMP = 3

125

—

fADC = 9 MHz, INPSAMP = 255

—

28.2

µs

— P Conversion time(5)

fADC = 20 MHz

(6), INPCMP = 1

0.65

——

µs

tADC_P

—

ADC power-up delay (time needed

for ADC to settle exiting from

software power down; PWDN bit = 0)

——

—

1.5

µs

(7)

— D ADC input sampling capacitance

—

2.5

CP1

(7)

— D ADC input pin capacitance 1

—

CP2

(7)

— D ADC input pin capacitance 2

—

RSW

(7)

— D Internal resistance of analog source

VDD_HV_ADC0 = 5 V ± 10%

—

0.6

VDD_HV_ADC0 = 3.3 V ± 10%

—

RAD

(7)

— D Internal resistance of analog source

—

IINJ

— T Input current injection

Current injection on one ADC

input, different from the

converted one. Remains

within TUE specification

−5—

INL

P Integral non-linearity

No overload

−1.5

—

1.5

LSB

DNL

P Differential non-linearity

No overload

−1.0

—

1.0

LSB

T Offset error

—

±1

—

LSB

T Gain error

—

±1

—

LSB

TUE

Total unadjusted error without

current injection

—

−2.5

—

2.5

LSB

TUE

Total unadjusted error with current

injection

—

−3—

LSB

VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = −40 °C to TA MAX, unless otherwise specified and analog input voltage from

VSS_HV_ADC0 to VDD_HV_ADC0.

AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which the precision is lost.

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