SPC560P34L1 datasheet(26/103 Pages) STMICROELECTRONICS

26 / 103 page

Introduction

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

26/103

Doc ID 16100 Rev 7

Digital part:

●

16 input channels

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4 analog watchdogs comparing ADC results against predefined levels (low, high,

range) before results are stored in the appropriate ADC result location

●

2 modes of operation: Motor Control mode or Regular mode

●

Regular mode features

–

ADC state machine managing 3 request flows: regular command, hardware

injected command and software injected command

–

Selectable priority between software and hardware injected commands

–

DMA compatible interface

●

CTU-controlled mode features

–

Triggered mode only

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4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)

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Result alignment circuitry (left justified and right justified)

–

32-bit read mode allows to have channel ID on one of the 16-bit part

–

DMA compatible interfaces

1.5.27

Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user

selected conditions without CPU load during the PWM period and with minimized CPU load

for dynamic configuration.

It implements the following features:

●

Double buffered trigger generation unit with up to 8 independent triggers generated

from external triggers

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Trigger generation unit configurable in sequential mode or in triggered mode

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Each trigger can be appropriately delayed to compensate the delay of external low

pass filter

●

Double buffered global trigger unit allowing eTimer synchronization and/or ADC

command generation

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Double buffered ADC command list pointers to minimize ADC-trigger unit update

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Double buffered ADC conversion command list with up to 24 ADC commands

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Each trigger capable of generating consecutive commands

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ADC conversion command allows to control ADC channel, single or synchronous

sampling, independent result queue selection

1.5.28

Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE-

ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring

external address and data pins for internal visibility. The NDI block is an integration of

several individual Nexus blocks that are selected to provide the development support

interface for this device. The NDI block interfaces to the host processor and internal busses

to provide development support as per the IEEE-ISTO 5001-2003 Nexus Class 1 standard.

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