ST7MC1K2 datasheet(318/371 Pages) STMICROELECTRONICS

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Figure 133. Typical IDD in SLOW vs fCPU

12.4.2

Wait and Slow Wait modes

Figure 134. Typical IDD in Wait vs fCPU

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Fcpu Mhz

Table 193.

Wait and Slow Wait modes

Symbol

Parameter

Conditions

Typ

Max(1)

Unit

IDD

Supply current in Wait mode(2)

(see Figure 134)

4.5V < VDD < 5.5V

fOSC =16MHz,

fCPU =8MHz

812

Supply current in Slow Wait mode(2)

(see Figure 135)

fOSC =16MHz,

fCPU = 500 kHz

3.5

Data based on characterization results, tested in production at VDD max. and fCPU max.

Measurements are done in the following conditions:

- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is

50%.

- All I/O pins in input mode with a static value at VDD or VSS (no load)

- All peripherals in reset state.

- LVD disabled.

- Clock input (OSC1) driven by external square wave.

- In Slow and Slow Wait mode, fCPU is based on fOSC divided by 32.

To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the peripheral power

consumption.

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Fcpu Mhz

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