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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7MC1K2 데이터시트(PDF) 337 Page - STMicroelectronics |
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ST7MC1K2 데이터시트(HTML) 337 Page - STMicroelectronics |
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337 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto Electrical characteristics 337/371 Figure 148. SPI slave timing diagram with CPHA = 0(1) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. Figure 149. SPI slave timing diagram with CPHA = 1(1) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. SS INPUT CPHA = 0 MOSI INPUT MISO OUTPUT CPHA = 0 tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tv(SO) ta(SO) tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB IN LSB OUT seenote2 CPOL = 0 CPOL = 1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 BIT1 IN SS INPUT CPHA = 1 MOSI INPUT MISO OUTPUT CPHA = 1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) tsu(SI) th(SI) MSB OUT BIT6 OUT LSB OUT see CPOL = 0 CPOL =1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 note 2 tc(SCK) HZ tv(SO) MSB IN LSB IN BIT1 IN Obsolete Product(s) - Obsolete Product(s) |
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