ST10F296 datasheet(56/346 Pages) STMICROELECTRONICS

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Internal Flash memory

ST10F296E

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XFlash interface control register (XFICR)

This register is used to configure the XFlash interface behavior on the XBus. It allows the

number of wait states introduced on the XBus to be set before the internal READY signal is

given to the ST10 bus master.

1ERER

Erase error

This bit is automatically set when an erase error occurs during a Flash

write operation. This error is due to a failure of a Flash cell that can no

longer be erased. This kind of error is fatal and the sector where it

occurred must be discarded. This bit has to be reset by software.

0ERR

Write error

This bit is automatically set when an error occurs during a Flash write

operation or when a bad operation setup is written. Once the error has

been discovered and understood, the ERR bit must be reset by

software.

XFICR (0xE E000h)

XBus

Reset value: 000Fh

Reserved

WS3WS2

WS1WS0

RWRWRW

Table 25.

XFICR register description

Bit

Bit name

Function

15-4

Reserved

3-0

WS[3:0]

Wait state setting

These three bits are the binary coding of the wait state number

introduced by the XFlash interface through the internal READY signal of

the XBus. The default value after reset is 1111, where up to 15 wait

states are set. Recommendations for the ST10F296E include:

For fCPU > 40 MHz: 1 wait state WS[3:0] = 0001

For fCPU ≤40 MHz: 0 wait state WS[3:0] = 0000

Table 24.

FER register description (continued)

Bit

Bit name

Function

Obsolete

Product(s)

- Obsolete

Product(s)

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